In times prior to the advent of large scale integration, the designer of computer logic has had complete flexibility in arranging logic circuitry to implement system and sub-system logic functions in central processing units, channels and control units employed in digital computing apparatus. A significant variety of design implementations has resulted from the exercise of this flexibility. Each of these implementations has its own special dependency on the ac characteristics of the individual circuits empolyed in the system.
The independence and flexibility characterizing the arrangements of the designer often led to unexpected system timing problems, complicated and complex problems in testing the circuitry, and a significant complexity and detail required for educating the field service personnel for such computing systems. However, it had the advantage of permitting the designer to use all techniques to obtain the best performance by employing the fewest number of circuits. The interface between the logic designer and the component manufacturer was reasonably well defined and the approach of the past could be supported in component manufacturing since the ac parameters such as rise time, fall time, individual circuit delay, etc., could rather readily be tested. With the advent of large scale integration, however, this well defined and reliably tested interface no longer exists. It has become impossible or impractical to test each circuit for all of the well known ac circuit parameters. As a result, it is necessary to partition and divide logic systems and sub-systems into functional units having characteristics that are substantially insensitive to these parameters. Large scale integration provides the ability for the logic designer as well as the component manufacturer to utilize the capacity for placing hundreds of circuits on a single chip of semiconductive material. Such an ability offers the potential for reducing power, increasing speed, and significantly reducing the cost of digital circuits.
Unfortunately, a number of serious considerations are involved before this potential can be achieved. For example, in a medium sized computing system having approximately 40,000 individual circuits, it has not been uncommon to effect 1500 or more engineering changes during the development period for the product. It is readily apparent that the implementation of such a significant number of engineering changes approaches the impossible when dealing with the lowest level modular unit of a computer which has hundreds of circuits contained within it.
Another area which must be considered as technology moves into the fabrication of large scale integrated functional units is the product testing required prior to its incorporation into a computing system. The subsequent diagnostic tests performed during field servicing as well as the simulation that is performed during design and manufacturing are factors for consideration in fabricating such functional units.
In the past, each individual circuit has been tested for the usual and normal ac and dc parameters. Access to the modular unit for applying the input test conditions and measuring the output responses has been achieved through a fixed number of input/output connection pins. However, in the realm of large scale integrated functional units, the same number of input/output pins are available, but there is considerably more circuitry.
Thus, in a typical module containing one hundred chips each having up to six hundred circuits with a three hundred circuit average, the module would contain at least 30,000 circits. Parametric testing of such a unit is not possible. If functional tests are attempted on such a unit, having the prior art logical design configurations, the extent of coverage of testing would be significantly low and the level of reliability for use in a computing system would also be significantly low. Accordingly, provision must be made for eliminating the dependencies of the past. Current logical systems must be avoided and new logic organizations must be utilized in computing systems if the advantages of large scale integration are to be optimized. Testing must be performed in a functional manner on these new logical units, be it at the chip level, the module level, or other level. This testing is accomplished by automatically generating tests that assure the proper operation of every logic element in the unit.
To solve the problems listed above, the logic system (Level Sensitive Scan Design) and methods of testing the logic system described in U.S. Pat. Nos. 3,783,254, 3,761,695 and 3,784,907 (fully identified earlier herein) were defined so as to be applicable to all levels of the hierarchy of modular units. The generalized logic systems described in the above patents have a single-sided delay dependency, avoid all race conditions and hazards and eliminate the normal and usual ac timing dependencies. The functional logical units are made solely dependent on the occurrence of the signals from plural system clock trains. This is accomplished by using clocked dc latches for all internal storage circuitry in the arithmetic/logical units of the computing system. This latch circuitry is functionally partitioned along with associated combinational logic networks and arranged in sets. The plural clock trains are synchronous but non-overlapping and independent. The sets of latch circuitry are coupled through combinational logic to other sets of latches that are controlled by other system clock trains or combinations of clock trains. One of the ways to accomplish this objective is to use a different system clock for each one of the sets of latch circuitry.
The logic system of the U.S. Pat. No. 3,783,254 incorporates another concept, aside from the single-sided delay dependency giving hazard and race-free operation. It provides for each latch circuit to include additional circuitry so that each latch functions as a shift register latch having input/output and shift controls that are independent of the system clocks and the system input/outputs. All of these shift register latches are coupled together to form one or more shift registers. Each has a single input, a single output and shift controls.
With this additional circuitry, all of the system clocks can be de-activated, isolating all of the latch circuits from one another, and permitting a scan-in/scan-out function to be performed. The effect is to reduce all of the sequential circuitry to combinational circuitry which is partitioned down to the level of multistage combinational networks. This permits automatic test generation to be performed for testing each circuit in the entire logical unit.
It has been found necessary to reduce sequential logic circuits effecitvely to combinational logic networks as the problem of automatic test pattern generation is more easily solved for the latter type of network. The concept of the above patent provides for the latches to be converted into shift register latches. When this is accomplished, the shift register latches are then employed to shift in any desired test pattern of binary ones and zeros where they are retained for use as inputs to the combinational networks. The results of the combinational logic are clocked into the latches and then shifted out for measurement and comparison to determine the functional response of the logical unit.
The functional testing of the logic system under test is carried out in two parts. The first part of the functional tests checks the operation of the shift register configured for scan-in/scan-out function. The second part of the functional tests checks the operation of the remainder of the logic system.
With all system clocks in an off condition, the shift function is checked for proper operation by scanning in the stimuli of a pattern of binary ones and zeros using the shift controls. A comparison is made of this scanned-in stimuli with the responses of the pattern propagated through the stages of the shift register. Any fault in the register may then be isolated.
The automatically generated stimuli of the test patterns are provided one at a time to the functional logical unit being measured. Each set of stimuli of a pattern is shifted into the register and also provided as input signals to the functional unit. The contents of the shift register latches are measured at the unit outputs against the expected responses of the particular test pattern, thereby obtaining an initial indication of the state of the storage circuits. The effect of scanning the test pattern into the shift register is to negate the past history of the sequential circuits to be combinational in nature.
In the test method, the stimuli supplied to the unit inputs as well as the unit generated inputs from the shift register latches propagate through the networks of combinational logic. One system clock is exercised gating the output from one logic network to the associated stages of the shift register. Employing the independent shift controls, the contents of the register are shifted out for comparison with the expected responses of the test pattern. By controlling the system clocks associated with predetermined logical networks, the performance of each of the networks in a functional logic unit may be ascertained. Repeating this procedure with additional test patterns from the automatic test generator provides a clear indication of the fault status of the unit.
To perform propagation delay testing, the logic system under test is set up to perform the dynamic ac measurements. The latch circuitry organized into sets is initialized. This is accomplished by shifting a test pattern into the latch circuits of the register using the scan access. Concurrent with the initialization of the latch circuitry, the test pattern is applied to the system inputs. The application of the test pattern to the system inputs and to the sets of latches involves the sensitizing of a selected path within the logic system under test. Such a path flows through a combinational circuit network and the effect is to condition the inputs to the individual circuits of the network so that when one of the primary inputs is changed, propagation of the change takes place through the particular sensitized path to a location for measurement. To effect a change, a primary input is altered. After a predetermined lapsed time folling the changing of the primary input, any change that has resulted at the output of the sensitized path of the combinational network is measured.
Generally, four types of sensitized paths must be considered for testing propagation delay. These include the path from a primary input through a combinational circuit network to a primary output. A second path is from a primary input through a combinational circuit network to a latch set which forms part of the shift register. A third path is from a latch set forming a part of a shift register through a combinational circuit network to a primary output and the fourth path is from one set of latches through a combinational circuit network to a second set of latches. A primary input as used in the context of testing is either a system input or a clock input provided at a particular time. The ability to shift test patterns into and out of the sets of latches arranged as a shift register using the independent scan access and controls coupled with the independence of the clock signals renders it possible to perform the dynamic testing of these types of paths for propagation delays.
Dependent on the particular path that has been sensitized for measurement of propagation delays, the measurement occurs either by direct observation or by exercising another clock train so as to gate the output of a combinational circuit network into a latch set. In this way, it may be shifted out using the scan access and controls for measurement. Thus, in those paths which run to a primary output, the measurement is performed directly. In those instances where the sensitized path runs to a latch set, the measurement is made by clocking the combinational circuit network into the set of latches, and then shifting out using the scan access and controls. In all instances, interrogation is made as to whether the output changed to a new value. If there had not been any change, then the propagation delay through the selected paths exceeds a predetermined value and the particular unit under test is rejected as being out of specification. On the other hand, if a change took place, an indication is provided that the propagation delay is within the particular specification and the unit is accepted.
In this manner, automatically generated test patterns are provided one at a time to the functional logic unit being tested for propagation delay. Each set of patterns is shifted into the register and also provided as input signals to the functional unit. By effecting a change in one of the system inputs or in one of the clock trains, a selected path is sensitized through at least a portion of the logical unit. Dependent on the portion selected, a measurement is made to determine if the requisite specification for propagation delays has been met. Repeating this procedure with a substantial number of test patterns from an automatic test generator, provides a clear indication of the propagation delays through the unit.
The use of these latches enables dc testing of the logic system to be performed. By controlling and measuring the maximum circuit delay through the combinational networks of the entire unit, an appreciation of the ac response for the unit is obtained. With such a system, the state of every latch in the logic system may be monitored on a single cycle basis by shifting out all the data in the latches to some sort of a display device. This may be accomplished without disturbing the state of the sub-system, if the data is also shifted back into the latches in the same order as it is shifted out.
The arrangement has the effect of eliminating the need for special test points in such a system and therefore enables a greater density of circuit packaging to be achieved. Another advantage for such a system is that it provides a simple standardized interface allowing greater flexibility in creating operator or maintenance consoles. The consoles are readily changeable without in any way changing the logic system. Diagnostic tests may be performed under the control of another processor or tester and, in addition, perform such functions as reset, initialization and error recording. One of the most significant advantages of this logic organization and system is that it enables marginal testing to be implemented by merely controlling the speed at which the system clocks operate. From this test data, it can be readily determined as to the speed of response of the functional unit and its possible area of future utilization.
One of the significant features of the Level Sensitive Scan Design System (LSSD) is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. Plural clock trains control groups of the shift register latches in the operation of the system. Independent accessing and controls are also provided for these latches for the independent scan-in/scan-out function to be performed.